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marvell. moving forward faster doc. no. mv-s106340-01, rev. b august 6, 2010 document classification: proprietary customer use cover 88em8080/88em8081 led power supply controller for flyback converters with power factor correction datasheet
document conventions note: provides related information or information of special importance. caution: indicates potential damage to hardware or software, or loss of data. warning: indicates a risk of personal injury. document status doc status: preliminary informat ion technical publication: 0.xx for more information, visit our website at: www.marvell.com disclaimer no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including phot ocopying and recording, for any purpose, without the express written permission of marvell. marvell retains the right to make changes to this document at any time, with out notice. marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the impli ed warranties of merchantability or fitness for any particular purpose. further, marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situati on if any such products failed. do not use marvell products in these types of equipment or applications. with respect to the products described herein, the user or recipient, in the absence of appropriate u.s. government authorizati on, agrees: 1) not to re-export or release any such information consisting of technology, software or source code controlled for national s ecurity reasons by the u.s. export control regulations ("ear"), to a national of ear country groups d:1 or e:2; 2) not to export the direct product of such technology or such software, to ear country groups d:1 or e:2, if such technology o r software and direct products thereof are controlled for national security reasons by the ear; and, 3) in the case of technology controlled for national security reasons under the ear where the direct product of the technology is a complete plant or component of a plant, not to export to ear country groups d:1 or e:2 the direct product of the plant or major component thereof, if such direct produ ct is controlled for national security reasons by the ear, or is subject to controls under the u.s. munitions list ("usml"). at all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this doc ument in connection with their receipt of any such information. copyright ? 1999?2009. marvell international ltd. all rights reserved. marvell, moving forward faster, the marvell logo, alaska , anyvoltage, dsp switcher, fastwriter, feroceon, libertas, link street, phyadvantage, prestera, topdog, virtual cable tester, yukon, and zj are registered trademarks of marvell or its affiliates. carrierspan, linkcrypt, powered by marvell green pfc, qdeo, quietvideo, sheeva, twind, and vct are trademarks of marvell or its affiliates. patent(s) pending?products identified in this document may be covered by one or more marvell patents and/or patent applications . 88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 2 document classification: proprietary august 6, 2010, preliminary information
88em8080/88em8081 led power supply controlle r for flyback converters with power factor correction copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 3 product overview the marvell ? 88em8080/88em8081 device is a high performance led power supply contro ller for flyback converters with output regulation and power factor correction. the 88em8080/8081 control algorithm uses average current mode control (acmc) for power factor correction (pfc) in led lighting applications with low harmonic distortion and good noise immunity. the marvell proprietary adaptive loop control achieves high power factor under high input voltage and low load conditions. through marvel l's innovative digital signal processing (dsp) solution, the led controller with the pfc function provides the customer with the smallest package, the lowest system cost, the lowest total harmonic distortion (thd) and the best power factor for led lighting applications. both devices work at fixed frequencies, 88em8080 at 60khz while 88em8081 at 120khz. the ic operates under continuous conduction mode (ccm) or di scontinuous conduction mode (dcm) or both combined together operating in mixed mode. the internal voltage loop compensation and current loop control guarantee system stability and thus reduce the exernal component count and costs. the 8-pin soic package further facilitates the application design process by saving board sp ace. the resultant simple system design and minimum cost makes 88em8080/88em8081 the ideal choice for led applications with pfc. figure 1 shows a reference schematic for a universal isolated led driver with pfc using the 88em8080/88em8081 device. general features ? mixed mode ? ccm and dcm operation ? average current mode control ? adaptive control loop achieves high power factor and low thd for a wide range of voltage and load conditions ? adaptive over current protection for universal voltage ? fixed switching frequency ? 1.2a (typical) driver capability ? minimal external components required ? under voltage lockout (uvlo) ? over voltage protection (ovp) ? thermal shutdown ? input line frequency range from 45hz to 65hz applications ? led home and facility lighting ? led street lamps figure 1: universal isolated led driver with pfc vin c14 fb isns sgnd pgnd vdd 4 u3 sw 5 7 8 1 2 3 88em8081 c9 r19 3 4 r11 1 2 d1 c5 r6 vdd d5 t1b 1 2 c4 r15 d4 1 2 r9 r16 r13 n l l1 hvdc c7 c10 r18 r17 c8 r7 r12 var1 f1 r5 c6 q1 c12 d10 rs1j c3 d9 c11 c13 ntc1 r23 r10 led + led - c2 r4 r8 r3 r1 r2 u2 ts321lt 1 2 pc1a d6 1 2 r22 r21 c1 12 3 vref 1 5 3 4 2 u1 tl431 p/o pc1a d7 d8 d2 d3 t1
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 4 document classification: proprietary august 6, 2010, preliminary information this page intentionally left blank
table of contents copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 5 table of contents table of contents .............................................................................................................. ......................... 5 list of figures................................................................................................................ ............................. 7 list of tables ................................................................................................................. ............................. 9 1 signal description ............................................................................................................ ........... 11 1.1 pin configurations .......................................................................................................... .................................11 1.2 pin descriptions ............................................................................................................ ..................................11 2 electrical specificati ons ..................................................................................................... ........ 15 2.1 absolute maximum ratings ........ ........................................................................................... ........................15 2.2 electrical characteristics ........................... ...................................................................... ...............................16 3 functional description........................................................................................................ ........ 19 3.1 overview .................................................................................................................... .....................................19 3.2 vdd ? bias power input ...................................................................................................... ...........................20 3.3 pgnd and sgnd ............................................................................................................... ............................20 3.4 sw ? switched pwm output for gate drive ............ .............. .............. ........... ........... ........... ............ ..............20 3.5 vin ? input voltage sensing ................................................................................................. ..........................21 3.5.1 brown-out protection ...................................................................................................... ..................21 3.6 fb ? output voltage / current feedback ...................................................................................... ..................21 3.6.1 fb ? over voltage protection (ovp) ........................................................................................ ........21 3.6.2 fb ? regulation ........................................................................................................... .....................22 3.6.2.1 output current regulation - isolated output ......................................................................22 3.6.2.2 output current regulation - non-isolated output ..............................................................22 3.6.2.3 output voltage regulation - isolated output ......................................................................22 3.6.2.4 output voltage regulation - non-isolated ou tput ..............................................................23 3.7 isns ? current sensing / over current protection .. .......................................................................... .............23 3.7.1 isns ? peak current sensing ........................ ....................................................................... ...........23 3.7.2 isns ? average current mode control ....................................................................................... .....23 3.7.3 isns ? adaptive over current protection ......... .......................................................................... .....23 3.7.4 ocp ? cycle by cycle over current protection ... ........................................................................... .23 3.8 mixed modes of operation .................................................................................................... ..........................24 3.9 compensation and adaptive control loop ................ .............. .............. .............. .............. .............. ...............24 3.10 over temperature protection................................................................................................ ..........................24 4 functional characteristics .................................................................................................... ..... 25 4.1 v dd characteristics .............................................................................................................. ..........................25 4.2 v fb characteristics for over voltage protection ........... ........................................................................ ..........27 4.3 switching frequency characteristics ......................................................................................... .....................28 4.4 over current threshold characteri stics...................................................................................... ....................29
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 6 document classification: proprietary august 6, 2010, preliminary information 5 design and applications information ........................................................................................ 31 5.1 overview .................................................................................................................... .....................................31 5.2 input voltage resistor divider on vin pin................................................................................... ....................32 5.2.1 brown-out protection ...................................................................................................... ..................33 5.2.2 layout guidelines ......................................................................................................... ....................34 5.3 output led current control .................................................................................................. ..........................34 5.3.1 non-isolated output led current control ............ ....................................................................... .....35 5.3.1.1 r1 and r2 resistor divider design....................................................................................36 5.3.1.2 rc filter design ........................................................................................................ .........36 5.3.1.3 design of operational amplifier circuit ..............................................................................36 5.3.2 low-cost led current control with non-isolated output.................................................................37 5.3.3 led current control with isolated output ...... ............................................................................ ......38 5.3.4 isolated led current control - circuit design ............................................................................. .....40 5.3.5 ntc compensation circuit desi gn .............. .............. .............. .............. .............. ............ ......... ........42 5.3.5.1 design equations ............... .............. .............. .............. .............. ........... ............ .......... .......43 5.3.5.2 simplified engineering design procedure ...... ....................................................................45 5.4 current sensing and over current protection ......... ........................................................................ ...............46 5.4.1 current sensing through isns pin .......................................................................................... ........46 5.4.2 average current signal and over power limitation .............. .............. .............. ........... ........... .........4 7 5.4.3 peak current and average current relationship .... ......................................................................... 48 5.4.4 cycle by cycle current protection through ocp pin. .......................................................................4 9 5.5 sw pin to mosfet gate ....................................................................................................... ........................51 5.6 vdd, signal (sgnd) and power (pgnd) grounds ................................................................................. .......51 5.7 non-isolated led driver ..................................................................................................... ............................53 5.7.1 non-isolated led driver schematic .................. ....................................................................... ........53 5.7.2 non-isolated led driver descr iption ....................................................................................... .........54 5.8 isolated led driver ......................................................................................................... ................................55 5.8.1 isolated led driver schematic ............................................................................................. ............55 5.8.2 isolated led driver description........................................................................................... .............56 5.8.3 12.5w universal isolated led dr iver test results .......................................................................... 57 5.8.3.1 efficiency and power factor............................................................................................. ..57 5.8.3.2 start-up waveforms ...................................................................................................... .....58 5.8.3.3 steady state waveforms.................................................................................................. ..58 6 mechanical drawings ........................................................................................................... ....... 59 6.1 mechanical drawings ......................................................................................................... .............................59 7 part order numbering/package marking .............. .................................................................... 61 7.1 part order numbering ........................................................................................................... .......................61 7.2 package markings............................................................................................................ ...............................62 a revision history .............................................................................................................. ............ 63
list of figures copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 7 list of figures figure 1: universal isolated led driver with pfc ................................................................................ .............3 1 signal description ............................................................................................................ ............... 11 figure 2: soic-8 pin diagram (top view)................ ......................................................................... ..............11 2 electrical specifications .... ................................................................................................. ............ 15 3 functional description........................................................................................................ ............ 19 figure 3: top level block diagram............................................................................................... ...................19 4 functional characteristics.................................................................................................... .......... 25 figure 4: i dd quiescent (idd_qst) vs. v dd ...................................................................................................25 figure 5a: i dd vs. v dd (v dd_on ) ........................................................................................................................25 figure 5b: i dd vs. v dd (v dd_on )........................................................................................................................25 figure 6a: i dd operation (idd_op) vs. temperature ........................................................................................26 figure 6b: i dd operation (idd_op) vs. temperature ........................................................................................26 figure 7: vdd on/off vs. temperature ............................................................................................ ...............26 figure 8: i dd vs. v fb ............................................................................................................................... .........27 figure 9: vfb_ovp vs. temperature ............................................................................................... ...............27 figure 10: vfb_ovp hysteresis vs. temperature ................................................................................... .........27 figure 11: vfb_ovp_latch vs. temperature ........................................................................................ ........27 figure 12: normal regulation reference (vfb_reg) vs. tem perature ...........................................................28 figure 13: switching frequency vs. temperature .................................................................................. ...........28 figure 14: over current (viover) vs. input voltage vin peak value)............. .............. .............. ........... .........2 9 figure 15: over current (viover) vs. temperature ................................................................................ .........29 5 design and applications information ........................................................................................... . 31 figure 16: internal block for zero-cross detection, brown- out protection ........................................................ .32 figure 17: peak detecting signal for predictive sinusoidal ac voltage........................................................... .33 figure 18: input voltage resistor divider layout guide lines ..................................................................... .......34 figure 19: non-isolated feedback loop schematic ........... .............. .............. .............. .............. .............. .........35 figure 20: low-cost, non-isolated led current control.. ......................................................................... .........37 figure 21: isolated led current control......................................................................................... ...................38 figure 22: isolated led current contro l with ntc compensation................................................................... .42 figure 23: the error amplifier output voltage (vc) vs. temperature .............................................................. .44 figure 24: current sensing circuit.............................................................................................. .......................46 figure 25: current sensing and over current protection waveforms...............................................................4 8 figure 26: current sensing and cycle by cycle over curr ent protection circuit ..............................................49 figure 27: sw pin layout guidelines ............................................................................................. ...................51 figure 28: vdd decoupling capacitor and ground layout guid elines .............................................................52 figure 29: 1w non-isolated led driver schematic ......... ........................................................................ ..........53
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 8 document classification: proprietary august 6, 2010, preliminary information figure 30: 12.5w universal isolated led driver schemati c........................................................................ ......55 figure 31: efficiency, power factor ............................................................................................. ......................57 figure 32: start-up at 115vac at full load ...................................................................................... .................58 figure 33: start-up at 230vac at full load ...................................................................................... .................58 figure 34: steady state at 115vac at full load .................................................................................. .............58 figure 35: steady state at 230vac at full load .................................................................................. .............58 6 mechanical drawings ........................................................................................................... ........... 59 figure 36: 8-lead soic mechanical drawing .............. ......................................................................... ............59 7 part order numbering/package marking................. ...................................................................... 61 figure 37: sample ordering part number .......................................................................................... ...............61 figure 38: package marking ...................................................................................................... ........................62
list of tables copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 9 list of tables 1 signal description ............................................................................................................ ................ 11 table 1: pin definitions ........................................................................................................ ...........................11 table 2: pin descriptions ....................................................................................................... .........................12 2 electrical specifications .... ................................................................................................. ............. 15 table 3: absolute maximum ratings ......................... ...................................................................... ...............15 table 4: electrical characteristics ........................ ..................................................................... .....................16 3 functional description........................................................................................................ ............. 19 table 5: functional summary ..................................................................................................... ....................19 4 functional characteristics.................................................................................................... ........... 25 5 design and applications information ........................................................................................... .. 31 table 6: comparison between critical transition mode and mixed mode controls ..... .............. ........... .........32 table 7: current sensing circuit........................... ..................................................................... .....................47 table 8: current sensing resistor selection reference . .......................................................................... .....47 table 9: efficiency and power factor test results ............................................................................... .........57 6 mechanical drawings ........................................................................................................... ............ 59 7 part order numbering/package marking................. ....................................................................... 61 table 10: 88em8080/88em8081 part order options ........... ....................................................................... .....61 table 11: revision history ...................................................................................................... ..........................63
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 10 document classification: proprietary august 6, 2010, preliminary information this page intentionally left blank
signal description pin configurations copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 11 1 signal description 1.1 pin configurations 1.2 pin descriptions table 1: pin definitions figure 2: soic-8 pin diagram (top view) 1 2 3 4 8 7 6 5 pgnd sgnd isns ocp sw vdd fb vin pin # pin name pin type pin description 1 pgnd gnd power ground 2 sgnd gnd signal ground 3 isns input current sense 4 vin input voltage input 5 fb input feedback 6 ocp input over current protection 7 vdd supply ic supply voltage 8 sw output switch
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 12 document classification: proprietary august 6, 2010, preliminary information table 2: pin descriptions pin # pin name pin function 1pgnd power ground ? connected to the source of the primary mosfet. ? the pcb trace from the power ground to the s ource of the primary mosfet must be kept as short as possible. ? to avoid any switching noise interruption on signal processing, pgnd and sgnd remain seperate inside the ic. 2sgnd signal ground ? must be connected to the power ground with the kelvin sensing connection (typically connected to the source of the external mosf et) so that sgnd has dedicated trace and connections and provides clean signal integrity. ? to avoid any switching noise interruption on signal processing, sgnd and pgnd remain seperate inside the ic. 3isns current sense ? used for current shaping and for over current protection. ? sense resistor varies for different loads. examples - 0.15 at 120w rated load and 0.6 for 30w rated load. 4vin voltage input ? connects to resistance divider at input ac line ?phase? to gnd. voltage applied is a half rectified sine wave scaled down by the input resistance divider. ? voltage input pin is a high impedance input pin. an impedance of 2m (typical) is recommended to be designed from the input ac ?phase? to gnd for the vin resistor dividor network to reduce the standby power. higher impedance is preferred with the right pcb design on this pin signal. ? this voltage input after comparing with an internal threshold reference is used to detect the zero-cross location of the input sine wave and is also used to synthesize (regenerate) the input sine wave. this regenerated sine wave is used for the current reference. ? brown-out protection function is also provided by this pin. a resistor devider with a 100:1 ratio from the highside resistor to the lowside resistor is corresponding to a ?brown-out protection? input voltage of 50v (rms). increasing that ratio will increase the ?brown-out voltage?. brown-out voltage is determined by r 6 , r 13 and r 16 as shown in figure 1 . refer to section 5.2 for further understanding. 5fb feedback ? the output voltage of 100% rated value is scaled to 2.5v at the fb pin. ? transition from soft-start to normal regulation is at 87.5% rated v fb . when fb pin voltage exceeds v fb_ovp , the ic shuts down the sw pin driver pulse. sw pin driver pulse recovers when fb pin falls below the reference voltage, v fb_reg . ? there is another ovp latch threshold (v fb_ovp_latch ) of 3.77v on the fb pin. when fb exceeds v fb_ovp_latch , latched over voltage shutdown occurs until another vdd power on resets the latch. ? the effective resistance between fb and gnd is 200k (typical). 6ocp over current protection ? used to turn off the mosfet when it is pulled as logic low
signal description pin descriptions copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 13 7vdd ic supply voltage ? nominal voltage is 12v and the under voltage lock out (uvlo) occurs when v dd < v dd_uvlo and the ic is turned off. ? the ic is turned on whenever v dd > v dd_on (typ. 11.9v). ? the maximum voltage on vdd is 16v. ? vdd should be clamped by a zener for protection in the system design. refer to ta b l e 4 for more details. 8sw switch ? pwm gate signal for the switch. ? it should be connected to the gate of external mosfet through a gate resistor. table 2: pin descriptions pin # pin name pin function
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 14 document classification: proprietary august 6, 2010, preliminary information this page intentionally left blank
electrical specifications absolute maximum ratings copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 15 2 electrical specifications 2.1 absolute maximum ratings table 3: absolute maximum ratings 1 note: stresses above those listed in absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. 1. exceeding the absolute maximum rating may damage the device. symbol parameter min max units v dd power supply (voltage to pgnd=sgnd) -0.3 18 v v isns voltage at isns pin -0.5 0.5 v v ocp voltage at ocp pin -0.3 5.5 v v vin voltage at vin pin -0.3 5.5 v v fb voltage at fb pin -0.3 5.5 v i sw driver current (instantaneous peak) 2 a ja thermal resistance 156.5 c/w t a operating ambient temperature range 2 2. specifications over the -40 c to 85 c operating temperature ranges are assu red by design, characterization and correlation with statistical process controls. -40 85 c t j maximum junction temperature 125 c t stor storage temperature range -65 150 c v esd esd rating 3 3. devices are esd sensitive. handling prec autions recommended. human body model, 1.5k in series with 100pf. 2kv
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 16 document classification: proprietary august 6, 2010, preliminary information 2.2 electrical characteristics table 4: electrical characteristics note: a 12v supply voltage is applied and the ambient temperature (t a ) = 25c. symbol parameter conditions min typ max units v dd supply v dd supply voltage 7.0 12 16 v v dd_on v dd power on threshold 11.9 v v dd_uvlo v dd power off threshold (uvlo) after v dd is powered up and running 7.0 v v dd_uvlo_hys v dd_uvlo hysteresis 4.8 5 v i dd_qst v dd quiescent current 1 v dd = 12v 95 a i dd_op v dd operating current v dd = 12v; c gate = 1nf f sw = 118khz v in =0 5.2 ma thermal shutdown t sd thermal shutdown 150 c t sd_hys hysteresis for thermal shutdown 25 c output gate driver v g_hi minimum gate high voltage 2 v dd = 12v c gate = 1nf sourcing 500ma 10.0 v v g_lo maximum gate low voltage 3 v dd = 12v c gate = 1nf sinking 500ma 2.0 v r dson gate drive resistance sourcing 120ma t=25 c 2.4 gate drive resistance sinking 120ma t=25 c 2.0 i sw_pk driver peak current c gate = 10nf v dd = 12v 1.2 a t r rise time c gate = 1 nf 35 ns c gate = 10 nf 125 ns t f fall time c gate = 1 nf 35 ns c gate = 10 nf 145 ns d max maximum duty cycle 88 %
electrical specifications electrical characteristics copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 17 d min minimum duty cycle 4 3% feedback/overvoltage v fb_reg normal regulation reference ic powered on 2.55 v v fb_ovp over voltage protection threshold at 120% of v fb_reg .3.04v v fb_ovp_hys over voltage protection hysteresis 0.49 v v fb_ovp_latch over voltage protection latch 3.77 v current sensing and current protection 5 v iover_th1 over current threshold zone 1 6 peak value of half-sine voltage at v in : 1.26 88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 18 document classification: proprietary august 6, 2010, preliminary information 4. if the duty cycle is less than 3% from the dsp calculati ons, one pwm cycle is skipped and this duty-cycle value is added to the next pwm duty cycle calculation. 5. to achieve almost constant power limit for the universal input range, current protection self-adjusts thresholds in four zones of input voltage levels. a margin of 50% compared to the rated current is considered for the threshold current values. 6. threshold of negative voltage drop across r sns due to instantaneous current 7. with input divider ratio of 1/100, these values are equivalent to 90 v rms functional description overview copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 19 3 functional description 3.1 overview the 88em8080/88em8081 is a high-performance power factor correction controller for single stage flyback led lighting applications with a minimum number of componen ts at a low cost. the following section outlines the functions of various input and output signals of the 88em8080/88em8081 device as listed below in table 5 . table 5: functional summary section pin name function section 3.2 vdd bias power for ic section 3.3 pgnd/sgnd power and signal ground is the return for power and signals section 3.4 sw gate drive output section 3.5 vin input voltage sensing and brown-out protection section 3.6 fb inverting input of an internal error amplif ier used for regulation of output voltage / current section 3.7 isns input current sensing used for providing pfc and for adaptive over current protection section 3.7.3 ocp over current protection used for cycle by cycle protection figure 3: top level block diagram dsp core 88em8080/8081 current amplifier mux switcher & adc current protection threshold selection zero cross detect power distribution and bandgaps startup setting or frequency setting over temperature gate driver current protection protection management clock isns fb vin i _over i _over v o_over t _o ve r v o_over sw ocp vdd oscillator fault driver disable pgnd sgnd output voltage level detect serial data interface state machine note ? i _over , v o_over , and t _over are the over current, over volt age, and over temperature signals respectively.
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 20 document classification: proprietary august 6, 2010, preliminary information 3.2 vdd ? bias power input the controller needs bias power which is recieved through the vdd and pgnd pins. the nominal voltage for the vdd pin is around 12 volts and the ic will start switching as long as the vdd voltage exceeds the v dd_on power-on threshold described in table 4, electrical characteristics, on page 16 . the pwm switched output at the sw pin is available after the ic is switched on. once powered up and switching has started, the vdd volt age can reach as low as 7 volts (typical), at which point the ic is switched off. this 7 volt th reshold is the under voltage lockout (uvlo) value. once vdd goes below the uvlo threshold voltage, vdd must climb back to the v dd_on threshold to start switching once again. the maximum voltage needs to be less than 16 volts which provides some margin from an absolute maximum vdd volt age rating of 18 volts. when the ic is not switching (less than 12 volts before turn-on and less than 7 volts after turn-on), the 88em8080/88em8081 draws very little quiescent current which has a typical rating of 95 a. during switching, the operating current fr om the vdd source is around 5.2ma. from a circuit design point of view, bias can be pr ovided initially from the rectified low frequency ac input. once the ic starts switching, bias power can be derived from the high frequency part of the circuit. as an example, an auxiliary winding on the fl yback transformer can be used to provide this high frequency power. it is nece ssary to rectify the high frequency ac from the auxiliary winding and to have necessary filtering to reduce the high frequency ripple at the vdd pin. this approach of providing high frequency bias power after turn-on will improve the efficiency of the bias power circuitry in the steady state. it should be noted th at during startup, at the instant of switching, the current drawn by the chip increases from 95 a to 5.2ma (typical). this sudden step load of bias power will tend to decrease the vdd voltage. if the vdd voltage falls below 7 volts due to this reason, the ic will go through another starting cycle. to prevent this hiccup, adequate energy storage (capacitor) needs to be provided. the ca pacitors across vdd and pgnd will help to keep the vdd voltage above 7 volts. care is also needed in the design of bias power circ uit from the rectified low frequency ac side. if a simple resistance is used to charge the capacitor across vdd and pgnd, the turn-on time could be longer. variations in the bias circuit design ma y be accommodated to meet the specified turn-on time. the under voltage lockout (uvlo) feature can be us ed to shut off the ic during a fault condition by forcing the vdd voltage to go below 7 volts. if t he fault is removed, vdd voltage can be allowed to increase to vdd_on and the ic will go through a ne w starting cycle. 3.3 pgnd and sgnd the 88em8080/88em8081 has separated the powe r ground pin (pgnd) and signal ground pin (sgnd) inside the ic to avoid any noise interruption during signal processing. the pgnd pin should be connected to the primary mosfet source pin and the connection trace should be as short as possible. the sgnd must be connected to the pg nd through a kelvin sensing connection trace to achieve a clean signal ground. 3.4 sw ? switched pwm output for gate drive the sw pin is the pwm output pin for the ic. the ic has an internal totem pole drive circuit to drive the gate of an external power mosfet through this sw pin. a gate resistor is recommended to provide damping in the external drive circuit and to minimize the parasitic ringing. the pwm output gate drive capibility is 1.2a (typical). if necessary , additional drive circuitry along with speed up circuitry can be added to the sw pin output for very high power levels.
functional description vin ? input voltage sensing copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 21 3.5 vin ? input voltage sensing the pfc function is implemented by sensing the input current wavefo rm and forcing the average of the input current to follow the input voltage sinusoidal waveform. a resistor divider is used between ac input and a primary reference ground to sens e the input voltage. the primary reference ground is connected to the 88em8080/88em8081 ic reference ground and to the source pin of the external switching mosfet q1 as in figure 1, universal isolated le d driver with pfc, on page 3 . the output of the resistor divider which is a half sinu soidal waveform is the input to the vin pin. by sensing the input voltage waveform at the vin pin, the controller can generate its own internal sinusoidal reference at the same frequency as the input. this is done by having an internal dc threshold (0.72 volts), a comparator and a zero -cross detection circuit. the details of the calculations are described in section 5.2 . it is recommended to use a high impedance divide r network between the ac line to reference ac ground to sense the input voltage at the vin pin. this will help to reduce the no load input power and will improve the efficiency in general. due to the vin pin being a high impedance input pin, a 10nf (typical) decoupling noise capacitor between it and ground is required. 3.5.1 brown-out protection vin pin is also used for the brown-out protection fu nction. a resistor divider of 100:1 ratio from the high voltage side corresponds to a brown-out protection input voltage of around 50v rms for the defined internal threshold of 0.72 volts. increasing the high voltage divider turns ratio will increase brown-out protection voltage. 3.6 fb ? output voltage / current feedback the 88em8080/88em8081 has an inte rnal current loop and output voltage/current loop to implement the pfc and the output voltage/current regu lating function. fb pin is the inverting input of a voltage error amplifier with 2.5 vo lts as the internal reference vo ltage. for steady state operation 100% of required output voltage/current is scaled to 2.5v at the feedback pin by external circuitry. for output current regulation, the much smaller voltage across the load current sensing resistor could be amplified to be 2.5v and then applied to the fb pin. during startup, when fb pin is below 87.5% of t he reference voltage, the pfc controller operates in soft-start mode. the internal voltage error amplifier switches over to normal regulation phase once the fb pin voltage reaches 87.5% of the reference value. 3.6.1 fb ? over voltage protection (ovp) over voltage protection is implemented through the fb pin. when the fb pin voltage exceeds vfb_ovp threshold voltage (refer to table 4, electrical characteristics, on page 16 ), the ic is switched off and no pwm output is available at sw pin of the ic.
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 22 document classification: proprietary august 6, 2010, preliminary information 3.6.2 fb ? regulation 3.6.2.1 output current regulation - isolated output the general application for 88em8080/88em8081 is fo r led current control. the led current is passed through a series sense resistor and the volt age across that resistor is proportional to the led current. this sense resistor needs to be very sm all to limit the power dissipation in the resistor. the sensed voltage is then amplified to have 2.5v at the full load current. it is applied to the tl431 type of device where the error voltage between the amplified voltage and tl431 device reference (2.5v) is amplified. an optocoupler can be used to pass the error information to the feedback pin fb on the primary side. in addition the primary current is sensed and the average current is adjusted to be sinusoidal (in phase with ac input voltage). t he amplitude of the primary current is adjusted to make the secondary led current constant at the de sired level. because this is a single stage pfc there will be second harmonic ripple at the output . output capacitors are added to reduce the output second harmonic ripple and also the high frequency switching ripple. the proportional and integral compensation within the ic make the system stable . the over voltage prot ection at the output can be achieved by clamping the output of tl431. it is well known that ctr of an optocoupler va ries with temperature and there is a ctr variation among different units of the same optocoupler. an ntc circuit can be designed to help reduce the effect of variation of ctr. the entire circ uit design of the ntc circuit is provided in section 5.3.5 . it is important to note t hat the ic has internal compensation for the loop stability. 3.6.2.2 output current regula tion - non-isolated output the application is similar to the isolated example ( section 3.6.2.1 ) except there is no optocoupler. the led current is passed through a series sense re sistor and the voltage ac ross that resistor is proportional to the led current. this sense resist or needs to be very small to limit the power dissipation in the resistor. the sensed voltage is then amplified to be 2.5v at the full load current. to reduce the number of components the amplifier ca n be eliminated. in this case, a higher valued sense resister should be used to ge t the sense voltage equal to 2.5v at full load. it is to be noted that this will reduce the over all efficiency of the led driver. to have over voltage protection, the output voltage also can be sensed and diode or'ed to the output of the current sensing circuit. initially voltage loop takes over because the led load needs a minimum voltage to turn on. the voltage from the current sensing side is designed to be higher than the voltage from voltage sensing diode during norma l operation. also the voltage sensing helps to limit the output voltage, if one of the leds becomes open for any reason. the proportional and integral compensation within th e ic make the system stable. 3.6.2.3 output voltage regulation - isolated output the output voltage is sensed through a divider re sistor and a tl431 type of device can be used to amplify the error voltage from a reference voltage. an optocoupler can be used to pass the error information to the feedback pin fb on the primary side for isolating the output. in addition, the primary current is sensed and the average current is adjusted to be sinusoidal (in phase with ac input voltage). the amplitude of the primary current is adjusted to make the secondary voltage constant at the desired level. because this is a single stage pfc there will be second harmonic ripple at the output. output capacitors are added to reduce the output second harmonic ripple and also the high frequency switching ripple. the proportional and integral compensation within the ic make the system stable. the over voltage protection at the output can be achieved by clamping the output of tl431. it is well known that current transfer ratio (c tr) of an optocoupler va ries with temperature and there is also a ctr variation among different units of the same optocoupler. an ntc circuit can be designed to help reduce the effect of variation of ctr.
functional description isns ? current sensing / over current protection copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 23 it is important to note that the ic has internal co mpensation for the loop stability. there is no need for external compensation. 3.6.2.4 output voltage regulat ion - non-isolated output when non-isolated, an opto-isolator is not necessary. the output voltage is sensed through the output divider and the output of the divider is connec ted directly to the feedback pin fb. the ic then controls the output voltage in the same way as for the isolated case. it is import ant to note that the ic has internal compensation for the loop stability. 3.7 isns ? current sensing / over current protection 3.7.1 isns ? peak current sensing the 88em8080/88em8081 led driver provides power factor correction (pfc) in addition to providing regulation. regarding the pfc function , the average input current is varied to be proportional to the input voltage. this way the av erage input current will be sinusoidal. this input current is the same as the primary mosfet current in a flyback circuit. therefore, the ic can sense the mosfet current and then use average current mode control to implement the pfc function. the voltage across the resistor in series with mosfet (connected between mosfet source pin and bridge diode negative dc terminal) is used as primary current sensing signal. the primary mosfet source pin is grounded to apply a pwm signal between the gate and the source. the current sense signal in series mosfet source therefore becomes negative with respect to ground. the ic uses this negative signal for input cu rrent control to provide the pfc function. 3.7.2 isns ? average current mode control the voltage across the primary current sense resistor is proportional to the peak value of switching current. an rc filter can be used to provide the av erage current. the output of the rc filter is then applied to isns pin. the internal current loop adjusts the du ty cycle so that average current is sinusoidal. the amplitude of the sinusoidal current is adjusted by the external voltage/current loop to achieve constant output load voltage/current. 3.7.3 isns ? adaptive over current protection the average current signal at the output of the rc fi lter is also used for over current protection. the ic has an internal current comparator with four diff erent internal thresholds for current protection on isns pin as the input voltage signal varies. the input current varies inversely with the ac input voltage. there are four different ocp thresholds at four different input voltage ranges. the different thresholds; v iover_th1 , v iover_th2 , v iover_th3 and v iover_th4 are detailed in table 4, electrical characteristics, on page 16 . with these four adaptive over current protection steps the ic provides almost constant power protection ov er the entire ac input voltage range. 3.7.4 ocp ? cycle by cycle over current protection the voltage across the primary current sense resistor is proportional to the peak value of switching current. this voltage can be used for cycle by cycle over current protection by the ocp pin. when the ocp pin is pulled low the ic will shut down an d there is no switched output signal at sw pin.
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 24 document classification: proprietary august 6, 2010, preliminary information 3.8 mixed modes of operation the 88em8080/88em8081 controll er operates in continuous conduction mode (ccm) or discontinuous mode (dcm) modes of operation. th e transformer primary inductance and the load determine the modes of operation. the ccm mode will have lower peak current than the discontinuous mode of operation. at high power levels ccm is recommended because of reduction of copper losses in the transformer and also the conduction losses in the primary mosfet. in addition ccm could reduce the input filter size. dcm mode may be recommended at lower power levels to reduce the turn-on switching losses a nd the primary fet losses due to reverse recovery time and charge of the output diode. 3.9 compensation and adaptive control loop the led current control is a fe edback control system. the bandwidth of the voltage loop for the single stage led feedback control system has to be much less than twice the line frequency to provide a high power factor and lo w thd. the entire f eedback system needs to be designed for high power factor and low thd at low line (90-132vac ) and high line (180-264vac). marvell has an internal proportional and integral gain control feature for the voltage loop due to marvell's dsp control technology. this means by sensing the input voltage, the ic sets pi control automatically to change the bandwidth for different ac input line ranges. this innovative adaptive feature will help achieve low thd and high power factor at all lines and loads. because of this proportional and integral control within the ic, no external compensation is required for non-isolated outputs. minimal external compensation is required for isolated outputs mainly for the compensation on the error amplifier (tl431) at the secondary side. this co mpensation network provides enough attenuation at 120hz so that the second harmonic ripple voltage from the sensed current signal is attenuated and not amplified. 3.10 over temperature protection the 88em8080/88em8081 ic has an internal ov er temperature sensing circuit. on over temperature, the fault detection signal shuts off the pwm switching output at the sw pin.
functional characteristics v dd characteristics copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 25 4 functional characteristics the following applies unless otherwise noted: v in = 60hz half-wave sinusoidal from 0v to the peak voltage (v pk ) given in the test conditions of each graph. t a = 25c. all measurement readings are typical. 4.1 v dd characteristics figure 4: i dd quiescent (i dd_qst ) vs. v dd test conditions: ? v in = 0v ? f sw = 118khz ? v fb = 0v ? c gate = 1nf ? v_i sns = 0v figure 5a: i dd vs. v dd (v dd_on ) figure 5b: i dd vs. v dd (v dd_on ) test conditions: ? v in = 0v ? f sw = 118khz ? v fb = 0v ? c gate = 1nf ? v_i sns = 0v test conditions: ? v in = 0v ? f sw = 118khz ? v fb = 2.4v ? c gate = 1nf ? v_i sns = 0v 0 10 20 30 40 50 60 70 80 90 100 024681012 vdd (v) idd ( a) 0 1 2 3 4 5 6 0246810121416 vdd (v) idd (ma) vdd falling vdd rising 0 1 2 3 4 5 6 7 0246810121416 vdd (v) idd (ma) vdd falling vdd rising
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 26 document classification: proprietary august 6, 2010, preliminary information figure 6a: i dd operation (i dd_op ) vs. temperature figure 6b: i dd operation (i dd_op ) vs. temperature test conditions: ? v dd = 12v ? v in = 0v ? f sw = 118khz ? v fb = 0v ? c gate = 1nf ? v_i sns = 0v test conditions: ? v dd = 12v ? v in = 0v ? f sw = 118khz ? v fb = 2.4v ? c gate = 1nf ? v_i sns = 0v figure 7: v dd on/off vs. temperature test conditions: ? v in = 0v ? f sw = 118khz ? f fb = 2.4v ? c gate = 1nf ? v_i sns = 0v 0 1 2 3 4 5 6 7 -40-20 0 20406080 temperature (c) idd (ma) 0 1 2 3 4 5 6 7 -40-20 0 20406080 temperature (c) idd (ma) 0 2 4 6 8 10 12 14 -40-20 0 20406080 temperature ( c) vdd (v) on off hysteresis
functional characteristics v fb characteristics for o ver voltage protection copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 27 4.2 v fb characteristics for over voltage protection figure 8: i dd vs. v fb figure 9: v fb_ovp vs. temperature test conditions: ? v dd = 12v ? v in = 0v ? f sw = 118khz ? c gate = 1nf ? v_i sns = 0v test conditions: ? v dd = 12v ? v in = 0v ? f sw = 118khz ? c gate = 1nf ? v_i sns = 0v figure 10: v fb_ovp hysteresis vs. temperature figure 11: v fb_ovp_latch vs. temperature test conditions: ? v dd = 12v ? v in = 0v ? f sw = 118khz ? c gate = 1nf ? v_i sns = 0v test conditions: ? f sw = 118khz ? v dd = 12v ? c gate = 1nf ? v in = 0v ? v_i sns = 0v 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.2 2.4 2.6 2.8 3.0 3.2 vfb (v) idd (ma) vfb down vfb up 0 1 2 3 4 -40-20 0 20406080 temperature (c) vfb (v) ovp_threshold recover threshold ovp threshold recovery threshold 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -40-20020406080 temperature (c) vfb (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 -20 0 20 40 60 80 temperature (c) vfb (v)
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 28 document classification: proprietary august 6, 2010, preliminary information 4.3 switching frequency characteristics figure 12: normal regulation reference (v fb_reg ) vs. temperature test conditions: ? v dd = 12v ? v in = 2v ? f sw = 118khz ? c gate = 1nf ? v_i sns = 0v figure 13: switching frequency vs. temperature test conditions: ? v dd = 12v ? v in = 0v ? v fb = 2.4v ? c gate = 1nf ? v_i sns = 0v 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 -40-20 0 20406080 temperature (c) vfb (v) 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 temperature (c) frequency (khz) fsw (8081) fsw (8080)
functional characteristics over current threshold characteristics copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 29 4.4 over current threshold characteristics figure 14: over current (v iover ) vs. input voltage v in peak value) test conditions: ? v dd = 12v ? f sw = 118khz ? v fb = 2.4v ? c gate = 1nf ? v_i sns = 0v 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 012345 vin (v) vcs (v) figure 15: over current (v iover ) vs. temperature test conditions: ? v dd = 12v ? f sw = 118khz ? v fb = 2.4v ? c gate = 1nf ? v_i sns = 0v 0 50 100 150 200 250 300 350 400 450 -40-20 0 20406080 temperature ( c) vcs (v) v in = 1.5v v in = 3v v in = 2.25v v in = 3.7v
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design and applications information overview copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 31 5 design and applications information 5.1 overview the 88em8080/88em8081 is a pwm controller for le d applications with pfc. flyback topology is used to simplify the two stage (front-end pf c and output stages) design to a single stage that includes power factor correction (pfc) and regulati on of the output. compared to the two stage structure, a single stage with pfc is a more cost effective solution for led lighting applications. the following sections provide guidelines for the appl ication design, component selection, and board layout in order to improve led application pe rformance with pfc based on the flyback topology. the 88em8080/88em8081 ic control algorithm uses average current mode control for power factor correction applications with low harmonic distorti on and good noise immunity. the ic senses the output current and forces it to follow the refere nce led current matching the design requirements. the chip also senses the primary current and forc es the average signal of the primary current to follow the sinusoidal current refer ence, therefore achieving power fact or correction. this is possible because the bandwidth of the outer current/voltage loop is much smaller than twice the line frequency. this ic implements the adaptive loop co ntrol so that the led power supply achieves high power factor even under high input voltage and low l oad conditions. the device also provides strong gate drive capability of 1.2a (typical). there are four analog input signals and one lo gic output signal for the 88em8080/88em8081 controller. 1. input voltage signal at vin pin is a half sinusoid al waveform. it is fed into the vin pin through the input voltage resistor divider. this is fo r the line frequency zero-cross detection for pfc. using the zero-crossing detector, the ic can pr edict the input sinusoidal waveform. the design of the input voltage divider and the design equations for the prediction of input sinusoidal voltage are described in the following section 5.2 .the signal at the vin pin also provides brown-out protection because of the minimum vin voltage requirement. this brown-out protection is described in section 5.2.1 . 2. input signal at fb pin is the output feedba ck signal through the output voltage resistor divider plus the compensation. for led cu rrent control, led current is se nsed and fed back to fb pin. an optocoupler can be used for isolation, if neces sary. this signal helps to obtain output voltage regulation. 3. input current sensing signal is derived from the sensing resistor to the isns pin. this is for the average current mode control to achieve a go od sinusoidal current waveform and high power factor. this average current signal is also used for over current protection. 4. input over current protection (ocp) signal is a l ogic signal instead of an analog signal. it is used to shut down the output at the sw pin when pulled low for cycle by cycle current limiting. the output signal from the 88em80 80/88em8081 is the pwm gate drive signal from the sw pin. the switching frequency on the 88em8080 device is fi xed to 60khz while the 88em8081 is fixed to 120khz. refer to the 88em8080/88em8081 application note located on marvell.com for more application details.
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 32 document classification: proprietary august 6, 2010, preliminary information the advantages of this device operating under mi xed mode control when compared to critical transition mode are shown in table 6 . 5.2 input voltage resistor divider on vin pin accurate peak detection signal and zero-cross det ection for regenerating the input sinusoidal voltage is the most important issue for a proper current shaping and total harmonic distortion (thd) improvement. a peak detecting pulse is generated af ter comparing the vin sinusoidal signal to an internal threshold reference of 0.72v (typical) as shown in figure 17 . if the threshold reference is too high, near the peak area, the calculation may lose accuracy because of the low slope. on the other hand, if the threshold reference is too low, there co uld be an error on zero-cross detection due to the possible distortions near the zero-crossing. for a universal input voltage range (85vac~270vac) the optimum accuracy would be achieved if the threshold level is around 30 of the line cycle. figure 16: internal block for zero-cross detection, brown-out protection table 6: comparison between critical tran sition mode and mixed mode controls critical transition mode control mixed mode ? ccm/dcm control high peak current on switch low peak current on switch high diode peak current at secondary side low diode peak current at secondary side variable switching frequency with lowest switching frequency at peak input voltage fixed switching frequency big transformer small transformer difficult to achieve high power easy to achieve high power high cost low cost ac in r a r b r c vin 88em8080 /8081 peak detecting pulse phase ( ) zero crossing power limit threshold selection brown-out protection predictive sinusoidal ac voltage v dcin v line_pk
design and applications information input voltage resistor divider on vin pin copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 33 the values for the sensing resistors r a , r b , and r c in figure 16 are selected to get proper sinusoidal ac voltage, under voltage lockout, and peak voltage detection. if the values are too small there will be higher power loss and if they are too big there might be pickup noise on the vin signal. the recommended values are shown in the following equation: equation (1) where r a + r b is recommended to be 1.8m ? and r c is selected as 18k ? . knowing (r a + r b ), r a and r b can be designed. for this input voltage resistor divider, the appr opriate combination based on the voltage / power rating of the resistors should also be considered. figure 17: peak detecting signal for predictive sinusoidal ac voltage as can be seen in figure 16 , the internal peak detecting circuit generates peak detecting pulse through the inside comparator which has a threshold voltage of 0.72v and external ac sensing resistors of r a , r b and r c . this pulse is processed in the dsp core to calculate the mid-point (peak point) and the zero-crossing point of the sinusoidal waveform. the phase angle of is calculated using the widths (m and n) of the high and low signals. equation (2) equation (3) equation (4) peak value of the sinusoidal waveform is calculated by the following equation: equation (5) 5.2.1 brown-out protection the signal that appears on the vin pin is a half sinusoidal voltage waveform and its peak value has to be higher than 0.72v for normal operation. w henever the vin voltage is less than 0.72v at the peak value, it is considered as a brown-out co ndition. during the brown-out condition, the ic generates a low duty cycle of 6% to protect the system. for the design shown in equation (1) the brown-out protection occurs at the ac input of 50v rms (72v peak, vin=0.72v). to adjust the brown-out protection point, the resistance value of r a , r b and r c can be changed. r a r b + r c ------------------ 100 1 -------- - 1.8 m 18 k ----------------- == v ( ) = v line_pk x sin half line cycle n mn v line_pk half line cycle peak detecting pulse v line_ pk v vin_br = 0.72v (typ.) ?? n 2 ? () = m 2 + () = mn ? () 4 ? = v line_pk v () sin () ? =
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 34 document classification: proprietary august 6, 2010, preliminary information 5.2.2 layout guidelines it is recommended that a 0.1nf?10nf capacitor (c c ) is connected between vin and ground for noise immunity. the layout of r b , r c and c c should be kept as close as possible to the vin pin, as shown in figure 18 to reduce noise pickup. r a should be kept as close as possible to the high voltage input. figure 18: input voltage resistor divider layout guidelines 5.3 output led current control the brightness and color of a led are functions of le d current. a constant current source driver for led current therefore helps in control of brightne ss and color. the led current is passed through a current sense resistor and the voltage across the se nse resistor is used as a feedback signal for led current control. reference de signs are presented in the following sections for isolated and non-isolated outputs for the control of led current using marvell 88em8080/88em8081 ic. fb ocp vdd vin isns sw pgnd sgnd r a r b r c c c keep layout of rb, rc and cc as close as possible to vin pin to keep high noise immunization 88em8080/81
design and applications information output led current control copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 35 5.3.1 non-isolated output led current control figure 19 shows a typical configuration for non-isolat ed output led current control. led current is sensed by the resistor r sen2 . the voltage across r sen2 is amplified by an ampl ifier u2. the output of the operational amplifier is connected to fb pin through a diode d 2 . a voltage loop is also added for voltage regulation at no load. the two feedback loops (output voltage and output current) are implemented in an or structure through d 1 and d 2 . during startup, the output voltage increases and mu st reach certain level before the led current can flow. the output voltage is fed back through the resistor divider (r 1 and r 2 ) and the diode d 1 . r 1 and r 2 are designed to limit the output voltage duri ng startup (with no led current) and when the led string is open. figure 19: non-isolated feedback loop schematic fb 88em8080/81 v out c o2 r sen2 r 1 r 2 d 1 d 2 r 3 r 4 r 5 c fb c cp leds n p n s2 d r2 r i = 200k u3 u2
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 36 document classification: proprietary august 6, 2010, preliminary information 5.3.1.1 r 1 and r 2 resistor divider design the following equation can be used for the design of r 1 and r 2 . equation (6) where v out_max is the output over voltage regulation poi nt during starting or under a no load condition, r 1 and r 2 are in k ? , v d1 is the voltage drop of the diode d 1 and v ref is the reference voltage inside the 88em8080/88em8081 ic. the nominal value of v ref is 2.5v. this equation takes into account of the internal leakage at fb pin. the leakage at the fb pin is equivalent to a 200k resistor. because the forward current of diode d 1 is less (less than 25ma) the voltage drop v d1 is about 0.1v to 0.3v depending on the di ode and the temperatur e of the diode. it should be noted that under steady state conditions the current loop should be active and not the voltage loop. therefore care must be taken in selection of r 2 to make sure that the voltage at the cathode of d 1 is less than the voltage at the cathode of d 2 under steady state conditions. 5.3.1.2 rc filter design in single stage pfc led applications, the output has twice the line frequency ripple which may trigger the ovp function through the voltage at the fb pin. an rc filter defined by r 3 and c cp , is designed to filter the twice the line frequency ripple embedded in the feedback signal. the cutoff frequency of the rc filter should be much lower than twice the line frequency. the following equation (7) is used for the design of r 3 and c cp . equation (7) in some situations the output current will be very low and the output capacitance could be selected to be a high value. in this case, twice the line fre quency ripple at the output will be very low and this rc filter may not be necessary. 5.3.1.3 design of operati onal amplifier circuit the dc gain of the non-inverting amplifier circuit is based on the following equation: equation (8) however, the average current through the le d is controlled by the following equation: equation (9) where, i avg is the average led current, v d2 is the voltage drop on the diode d 2 and k u2 is the dc gain of the operational amplifier circ uit. from equation (9) the required k u2 can be determined. r 5 and r 4 are designed from equation (8). v out _max r 1 ----------- -------------- - v d 1 1 r 1 ----- - 1 r 2 ----- - + ?? ?? ? 1 r 1 ----- - 1 r 2 ----- - 1 200 -------- - ++ --------------- ------------------ ----------------- ---------------- - v ref = 1 2 r 3 c cp ----------- ---------- - 100 hz ? k u 2 1 r 5 r 4 ----- - + ?? ?? = i avg r sen 2 k u 2 () v d 2 ? v ref =
design and applications information output led current control copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 37 5.3.2 low-cost led current control with non-isolated output one can have a cost effective desi gn by not having the operational amplifier in the output current feedback loop. the circuit is shown in figure 20 . figure 20: low-cost, non-isolated led current control in this case, the voltage across r sen2 is directly connected to vfb pin through the filter r 3 and c cp and the diode d 2 but without the operational amplifier u2 . also it should be noted that r sen2 has to be selected so that the voltage across it is higher than 2.5v (by a diode drop) under steady state conditions. because of this condition, r sen2 will be of a higher value than when the operational amplifier is present and there will be a significant power loss in the r sen2 resistor. the efficiency of this led driver circuit will be lower than that of application circuit in figure 19, non-isolated feedback loop schematic, on page 35 . the following equation can be used for the design of r 3 in addition to equation 7. equation (10) where, i avg is the average led current, v d2 is the voltage drop on the diode d 2 , v ref is the internal reference of the 88em 8080/88em8081 ic, and resistors r 3 and r 4 are in k ? . fb 88em8080/81 v out c o2 r sen2 r 1 r 2 d 1 d 2 r 3 c fb c cp leds n p n s2 d r2 r i = 200k u3 r 4 i avg r sen 2 () v d 2 ? v ref 1 r 3 r 4 ----- - r 3 200 -------- - ++ ?? ?? =
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 38 document classification: proprietary august 6, 2010, preliminary information the following equation can be used for the design of r 1 and r 2 . equation (11) where, v out_max is the maximum output voltage, vd1 is the voltage drop on the diode d1, and resistors r 1 , r 2 and r 4 are in k ? . a reference design for a cost effective n on-isolated led driver is presented in section 5.7 . 5.3.3 led current control with isolated output the typical isolated output cu rrent control is shown in figure 21 . figure 21: isolated led current control figure 21 shows a typical configuration for led current control when the output is isolated from the ac input. the current through the led also passes through the resistor r8 and the voltage across r8 is used for output current sensing and for led current control. in order to reduce the power dissipation in the current sensing resistor, r8 could be selected to be a low value such as 0.1 ? . the voltage across r8 at 500ma steady state current is 50mv. this current sense voltage across r8 is amplified by the non-inverting amplifier u2 and is applied to the inverting input of the u1 circuit. typically, the tl431 ic is used for u1. u2 is necessary to amplify the sense voltage to 2.5v at the steady stat e led regulated current. this is because the non-inverting input of u1 has a reference voltage of 2.5v nominal. the u1 device is used to v out _max v ref 1 r 1 200 -------- - r 1 r 2 ----- - r 1 r 4 ----- - +++ ?? ?? v d 1 1 r 1 r 2 ----- - + ?? ?? + = vin c14 fb isns ocp sgnd pgnd vdd 4 u3 sw 5 7 8 1 2 6 3 88em8081 c9 r19 3 4 r11 1 2 d1 vdd c4 hvdc r5 c6 q1 d9 c11 c13 r23 led + led - c2 r4 r8 r3 r1 r2 u2 ts321lt 1 2 pc1a fod817a d6 1 2 r22 r21 c1 12 3 vref 1 5 3 4 2 u1 tl431 v out input voltage from rectifier bridge i eopto t1 v c r12 r7 c8 v out_u2
design and applications information output led current control copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 39 generate an error voltage of v c at the output after comp aring the output voltage of u2 to the internal reference voltage of u1. an optocoupler is connected betwe en the output (led+) and the u1 error voltage output through a resistor r23. the current through the optocoupler is a function of error voltage at the output of tl431and is varied until the output voltage of u2 is equal to u1 reference voltage of 2.5v. the current through the opto-transistor and resistor r11 is proportional to the opto-diode current by a factor of current transfer ratio of the optocoupler. the voltage across r11 is applied as input to fb pin. therefore, the voltage at the fb pin is a functi on of the error voltage output of u1.the voltage at the fb pin controls the duty cycle of the drive signal to the external mo sfet q1. the switching current of q1 is sensed by the voltage across resi stor r5. at steady state conditions the fb pin voltage will be 2.5v which is equal to the nominal value of internal reference for 88em8080/88em8081 ic. the voltage across r5 is filtered and the filtered vo ltage is proportional to the average current. the duty cycle is varied so that the average of the input current through the isns pin follows the ac input voltage. the amplitude of the ac sinusoidal i nput current is varied to adjust the output voltage, therefore adjusting the led current until the output voltage of u2 equ als the reference voltage of u1 (2.5v, typical). during startup, the fb pin voltage is zero and the dut y cycle at the sw pin is 6% (typical). soft start is provided until feedback voltage reac hes 2.1v which is 87.5% of the reference voltage of u3 (2.5v, typical). during the time the voltage at fb pin rise s to 2.1v, the internal current reference increases linearly. the internal current reference determines how fast the power is delivered to the secondary side in addition to other circuit parameters. theref ore the soft start time is the duration for internal current reference to raise linearly. when the fb pi n reaches 2.1v, the internal feedback loop starts closed loop operation to eventua lly reach steady state. it is to be noted that leds will not conduct until the voltage across them reaches a minimal valu e. this means the led load is open circuited during startup. the voltage across t he output capacitors c11 and c13 is zero initially at starting. the output capacitors c11 and c13 will get charged rather quickly and the output voltage could overshoot the steady state value. during starting condition when leds are no t conducting or if the led string is open circuited, the output voltage across the led string may go higher than the normal steady state value and the zener d6 will be conducting. the output voltage of u1 is equal to the zener voltage. once the leds starts conducting th e output voltage of u1 starts decreasing and will come to a steady state value at which point the voltage across d6 will be much lower than the zener conduction voltage. if the ambient temperature is increased, the ctr of the optocoupler will become less, then more current through the optodiode becomes necessary for led current regula tion. this means the output voltage of tl431 will be lower than the steady state voltage at the lower ambient. if the ambient is decreased, tl431 voltage will be higher than the steady state voltage at the higher ambient. the design of the tl431 should be such that the zener diode d6 should not conduct during normal operation at any temperature. in addition th e output voltage of tl431 cannot go below 2.5v for any reason during steady state operation.
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 40 document classification: proprietary august 6, 2010, preliminary information 5.3.4 isolated led current control - circuit design the relation between output current signal and the reference voltage of u1 is provided by the following equation: equation (12) where v refu1 is the tl431 reference voltage and is equal to 2.5v nominal, i ledavg is the average current through the led. r 8 is selected to be a low value so that the power dissipation is minimum. for the reference design it is 0.1 ? . one can select r 2 and r 3 from the above equation after selecting r 8 since v refu1 is equal to 2.5v. c11 and c13 are selected so that the second harmonic ripple at the output is reasonable. the zener diode d 1 is selected to be 4.7v so that the volt age at the fb pin cannot exceed the rated maximum voltage for the fb pin. the output voltage of u1 error amplifier (v c ), and the secondary side optocoupler diode current are related by the following equation: equation (13) where v fd is the forward voltage drop of opto-coupler diode and is about 1v. v c is also related to the fb pin voltage or the re ference voltage of u3 by the following equation: equation (14) where v fb_reg is the reference voltage of u3 and ctr is the current transfer ratio of optocoupler. at steady state no load condition, the secondary si de error amplifier enters into positive saturation status because of no current feedback signal. therefore, the output voltage v c increases to the maximum clamp voltage v zd6 as pointed out in the previous section. v zd6 should be higher than normal operation voltage of v c to keep enough margin. then the no load output voltage will increase until the fb pin voltage reaches 2.5v. the following equation can be used to calculate the no load output voltage. equation (15) v o_noload is also equal to the maximum voltage when the led string is broken or when the sense line is open. the following equation is provided to calculate the output over voltage protection point. equation (16) v refu 1 r 2 r 3 + r 3 ------------------ i ledavg r 8 = i sf v o v fd ? v c ? r 23 -------------------- --------------- - = v o v fd ? v c ? r 23 ------------------ ----------------- - ctr r 11 v fb _reg = v o _noload v fd ? v zd 6 ? r 23 --------------- ------------------ ----------------- ------------ - ctr r 11 v fb _reg = v o _ovp v fd ? v zd 6 ? r 23 ------------------ ------------------ ---------------- - ctr r 11 v fb _ovp =
design and applications information output led current control copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 41 at ovp condition the error amplif ier output voltage increases to v zd6 . it is pointed out that the primary fb pin voltage reaches the ovp threshold v fb_ovp (which is about 3v) when the output voltage increases to ovp level. this ovp condi tion can occur with a low output capacitance and high output ripple. the steady state output at no load can also be calculated using the following equation which depends on the normal operation voltage v c of the tl431 error amplifier at nominal full load condition and v zd6 . equation (17) it is important to note that v c varies with temperature and will also vary from unit to unit of the optocoupler. the transfer function of tl431 amplifier circuit is: equation (18) where v out_u2 is the output voltage of the amplifier u2 as shown in figure 21 . the values of c 1 , r 21 and r 22 are selected in such a manner that there is enough dc gain for the average current feedback signal. at the same time there should be enough attenuation at 120hz so that the second harmonic ripple voltage from the sensed current si gnal is attenuated and not amplified. therefore the low frequency zero should be placed far below twice the line frequency (<20hz). v o _noload v o v zd 6 v c ? + () = hs () v c s () v out _u2 s () ------------------ ----------- 1 sc 1 r 21 + sr 22 c 1 ------------------- ------------------- - ==
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 42 document classification: proprietary august 6, 2010, preliminary information 5.3.5 ntc compensation circuit design the secondary side error amplifier output voltage v c varies between the maximum value v zd6 and the minimum value 2.5v (u1 (tl431) minimum suppl y voltage). from equatio n (13) it can been seen that the variation of v c depends on the tolerance of r 11 and r 23 value, v fb reference voltage and ctr value of optocoupler. but the ctr value of optocoupler has a wide variat ion from unit to unit and also with temperature. for example, the relative ctr of fod817 form fairchild changes from 105% to 55% with ambient temperature from 0oc to 110oc. if ambient temperature increa ses, the ctr of optocoupler decreases, which results in a lower value for v c . when ambient temperature is over 110oc, the v c voltage could reach the minimum limit value of 2.5v. then the power system will be out of regulation. it is pointed out that 0oc and 110o c are selected for illustration only. at 0oc v c would increase from the value at room temperature. if it is high enough zener d 6 would conduct and the power system is out of regulation. in order to keep v c at a reasonable range (below zener d 6 voltage and above 2.5v with a margin) a ntc compensation circuit, shown in figure 22 , is introduced. an actual reference design is shown for illustration of ntc compensation. this com pensation circuit is composed of a ntc resistor ntc1, resistor r10 and r23 instead of resistor r23 only. figure 22: isolated led current control with ntc compensation vin c14 0.1 f fb isns ocp sgnd pgnd vdd 4 u3 sw 5 7 8 1 2 6 3 88em8081 c9 0.1 f r19 20.5 ? 1/8w 3 4 r11 1.24k 1 2 d1 4.7v 500mw vdd c4 22 f 25v hvdc r5 1.0 ? 1/4w c6 100pf q1 650v 4.5a d9 stps3150rl c11 330 f 35v c13 330 f 35v ntc1 33k r23 3.01k r10 4.02k led + led - c2 1.0 f 35v r4 4.99k r8 0.1 ? r3 4.99k r1 4.99k r2 243k u2 ts321lt 1 2 pc1a fod817a d6 15v 500mw 1 2 r22 10k r21 4.99k c1 1.0 f 50v 12 3 vref 1 5 3 4 2 u1 tl431 +25.0 vdc, 500ma (nominal) input voltage from rectifier bridge i eopto t1 c8 0.047 f 50v r7 187 ? r12 200 ? p/o pc1a v c
design and applications information output led current control copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 43 5.3.5.1 design equations with ntc compensation circuit, the total equivalent resistance decreases when ambient temperature increases and will compensate for th e variation of the ctr with temperature and maintain v c at a narrow range. similar effect take s place when the ambi ent temperature is decreased. the following two equations at 25oc and 110oc ambient temperature c ondition are used for selection of resistors r10 and r23 values. equation (19) equation (20) where, r ntc1_25 and r ntc1_110 are the resistance value of ntc1 at 25oc and 110oc ambient temperature. ctr_25 and ctr_110 are the ctr va lues of optocoupler at 25oc and 110oc ambient temperature and v c_25 and v c_110 are the actual output voltages of u1 amplifier at 25oc and 110oc ambient temperatures. in the following, v c is assumed to be constant at 25oc and 100oc for the selection of resistors r10 and r23. once the resistors ar e selected, the variation of v c at 25oc and 100oc can be calculated. equation (21) equation (22) equation (23) equation (24) equation (25) equation (26) equation (27) r10 can then be calculated from the following equation: v o v fd ? v c _25 ? r 23 r ntc 1_25 r 10 r ntc 1_25 r 10 + --------------------- --------------- - + ------------------ ------------------ --------------- - ctr _25 r 11 v fb _ref = v o v fd ? v c _110 ? r 23 r ntc 1_110 r 10 r ntc 1_110 r 10 + --------------------- ------------------ + ------------------ ---------------------- -------------- ctr 110 r 11 v fb _ref = v c _25 v c _110 v c == a v fb _ref r 11 v o v fd ? v c ? () ------------------- --------------------- --------------- = bctr _110 ctr _110 ? = cr ntc 1_25 r ntc 1_110 + = dr ntc _25 r ntc _110 ? = ebad + = f 4 e br ntc 1_25 r ntc 1_110 =
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 44 document classification: proprietary august 6, 2010, preliminary information equation (28) r23 can then be calculated from the following equation: equation (29) marvell provides an excel spread sheet tool for the required ntc compensation circuit selection to meet design requirements. the selection of a differ ent value for ntc part, will provide diffent values for r10 and r23. the excel spread sheet tool will help calculate variation of v c with temperature. the designer can then select a suitable nt c value to minimize the variation of v c . figure 23 shows the variation of v c with temperature for a 25v, 500ma output design with 33k ntc part. it is evident that the variation of v c voltage is small when ambient temperat ure changes from 0oc to 120oc. this clearly shows that the ntc comp ensation circuit can be used effectively to compensate for the tolerance of the components and also for the wider va riation of ctr of the optocoupler. a reference design for an isolated led driver is presented in section 5.8 . figure 23: the error amplifier output voltage (v c ) vs. temperature r 10 bc ? bc () 2 f ? + 2 e ----------------------------------------------------------------------- - = r 23 ctr _25 a -------------------- - r 10 r ntc 1_25 r 10 r ntc 1_25 + --------------------- --------------- - ? = 10 11 11 12 12 13 13 14 14 15 15 0 102030405060708090100110120 temperature (c) voltage (v)
design and applications information output led current control copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 45 5.3.5.2 simplified engineering design procedure in the previous section, by assuming v c_25 = v c_110 , values for resistors r23 and r10 are estimated by solving the two simulataneous equations 18 and 19. the simplified procedure can be used to get the estimates of r23 and r10. the steps are as follows. 1. knowing the zener value of d6, one can estimate v c_25 . for example, if d6 is a 15v zener, one can choose 11 volts for v c_25 . this provides 4v nominal margin for the zener not to conduct. 2. once v c_25 is known, equation 18 is solved to get the estimate for (r c ) = 3. assuming and to get the value of r23 and r10. 4. an ntc can be selected such that, r ntc1_25 is about 5-10 times the value of r10 and r ntc1_25 is about 1/5 - 1/10 the value of r10. 5. v c_110 can then be calculated from equation 19. 6. v c_110 should be in the allowable range for the u2 (tl431) and no conduction for zener d6. for this example, the voltage range for v c_110 should be around 5v to 10v. this will satisfy the minimum requirement for v c (not less than 2.5v) with a margin. 7. this process can be repeated until v c_110 is in the allowable range. r 23 r ntc 1_25 r 10 r ntc 1_25 r 10 + ------------------------------------- - + r 23 r c 2 ------ - = r 10 r c 2 ------ - =
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 46 document classification: proprietary august 6, 2010, preliminary information 5.4 current sensing and over current protection 5.4.1 current sensing through isns pin the current sensing circuit is illustrated in figure 24 . the voltage drop on the current sense resistor should be kept very small in order to reduce the power consumption on the sense resistor. in flyback topology, the drain to source current flows throu gh the transformer primary, mosfet and current sense resistor (r sen ). the average current mode control single stage solution uses two signals: the peak current signal to avoid the transformer satura tion including a short circuit condition, and the average current sense signal to achi eve pfc operation. the voltage drop (v sen ) across resistor (r sen ) represents the flyback peak current signal. the voltage of (v cs ), after r cs and c cs low pass filter, represents the average current signal of the primary si de of the flyback converter. figure 24: current sensing circuit fb drain vdd n p n s2 d r2 r sen vin c sen isns sw sgnd c cs r cs1 d sn r sn c sn q1 v sen v cs pgnd v out c in v dcin 88em8080/81 r cs2 u3
design and applications information current sensing and over current protection copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 47 the resistor (r sen ) should be designed as the example in table 7 where r sen is designed for a 60w power supply. table 8 shows the reference value of the current sensin g resistor for different input power levels. in the practical design, the current sensing resistor value could be fine tuned around the value shown in the table based on the specification and th e primary inductance of the flyback transformer . 5.4.2 average current signal and over power limitation the peak current is sensed as the voltage across the sense resistor. to convert flyback peak current into an average current signal, an rc filter is required as described in the previous section. figure 25 shows how the addition of the filter will resu lt in an average current signal. this average current signal, v cs is fed back onto the isns pin and used to achieve a sinusoidal current waveform by an internal current control loop. it is also used to achieve power limitati on. the corner frequency of the rc filter is recomm ended approximately 1/10~1/6 of the switching frequency. the recommended value for r cs1 is 187 ? , r cs2 is 200 ? . r cs1 and r cs2 are used for the purpose of blocking excessive negative and surge voltages. a single stage pfc operates at 120khz (typical) using the 88em8081 device. c cs is designed as 47nf which results in a corner frequency of 18hz. the corner frequency of the low pass filt er is defined by the following equation; equation (30) u3 is designed to perform over power limitation a ccording to different over current thresholds as shown in table 4, electrical characteristics, on page 16 . the adaptive over current and hence adaptive over power protection feature is described in section 3.7.3 table 7: current sensing circuit input power p in 60w minimum input voltage v in_min 85v maximum average input current 1a over current threshold zone 1 v iover_th1 0.39v over current margin i margin 30% current sensing resistor calculation 0.30 ? current sensing resistor selection r sns 0.30 ? i in_max 2 p in v in_min ---------------- - = r sns v iover_th1 i in_max 1 i min arg + () ---------------------------------------------------- - = table 8: current sensing resistor selection reference input power (w) 10 30 60 120 current sensing resistor ( ? ) 1.0 - 2.0 0.50 - 0.70 0.25 - 0.35 0.12 - 0.15 f corner 1 2 r cs 1 c cs -------------- ----------- - =
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 48 document classification: proprietary august 6, 2010, preliminary information figure 25: current sensing and over current protection waveforms 5.4.3 peak current and aver age current relationship the relationship between the flyback peak and the aver age current signals is der ived in this section. figure 25 explains this in detail. the peak to peak ripple current through the rsen resistor is given by the following equation. equation (31) the average current sensing signal across rs en during the mosfet switching on time is... equation (32) the average current sensing si gnal during the whole switchin g cycle can be calculated as equation (33) leading edge current gnd t on power limit ocp v cs v sen v cs avg v sen avg switching period v sen t on pk v cs avg v sen avg i ins v line d l m f s ------------- -------- - = v sen avg v senpk i ins 2 ----------- - r sen ? = v cs avg v sen avg d =
design and applications information current sensing and over current protection copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 49 5.4.4 cycle by cycle current protection through ocp pin the voltage across rsen and the ocp pin are used fo r cycle by cycle over current protection. this protection helps to avoid the transformer saturation. a circuit consisting of an npn transistor q2 with a low base to emitter parasitic capacitance is recommended for the design as shown in figure 26 . the sensing voltage through r sen should trigger and turn on the tr ansistor q2 during the over current condition. q2 then pulls the ocp pin to lo w and turns off the gate signal to the external mosfet. for the design of the protection circuit a -2mv /c (typical) temperature coefficient of v be should be considered. the lowest voltage (v be ) will be set at the junction temperature of 80c. figure 26: current sensing and cycle by cycle over current protection circuit at 80c, the base to emitter volage can be calcuated from the following equation equation (34) the highest v be voltage occurs when the junction temperature is -25c. equation (35) fb drain vdd n p n s2 d r2 r sen vin c sen isns sw sgnd c cs r cs1 d sn r sn c sn q1 v sen v cs pgnd v out c in v dcin 88em8080/81 r cs2 u3 r 2 r 1 q2 ocp r 3 v be 0.65 v 2 mv 80 25 ? () 0.54 v = ? ? v be 0.65 v 2 mv 25 ?25 ? () 0.75 v = ? ?
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 50 document classification: proprietary august 6, 2010, preliminary information the voltage v be should have tolerance margin to select the resistor, r sen . r sen can be selected from the following equation. equation (36) the minimum saturation current point of i lim for the transformer should satisfy: equation (37) i lim should have enough margins considering transformer saturation condition at lower ambient temperature. r 1 and r 2 act as voltage dividers to setup the right current limitation threshold. r 2 controls base current of the transistor q2. r 1 helps to discharge the parasitic capacitance of the transistor. the value of r 1 is recommended as 500~2k ? , r 2 as 500~2k ? and r 3 as 10k ? where r3 is connected between the collector of q2 and ocp. a capacitor in parallel with the r sns resistor is used to filter the noise for this ocp circuit to function properly. when the mosfet turns on, external c oss of the mosfet starts discharging. this causes the leading edge spikes of current and increases switching loss. figure 25 shows that this spike of current causes unwant ed over current protection. this phenomenon can be avoided by adding one capacitor, c sen . the leading edge current timing is less than 300ns (typical). c sen is recommended to have a value of 0.22 f/25v. the capacitive reactance of c sen should be far less than r sen for proper filtering of this leading edge current spike. r sen 0.50 v i ds peak --------------- - i lim 0.75 v r sen -------------- r 1 r 2 + () r 1 -------------- --------- =
design and applications information sw pin to mosfet gate copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 51 5.5 sw pin to mosfet gate the 88em8080/88em8081 provides a 1.2a (typical) drive current, which is the strongest driver capability in comparison with the other similar pa rt on the market. a gate resistor of about 20 ? is used between the sw pin and the gate of the external mosfet. the gate driver loop is subject to fast rise and the layout trace should be kept as short as possible in order to minimize the parasitic inductance, as shown in figure 27 . figure 27: sw pin layout guidelines 5.6 vdd, signal (sgnd) and power (pgnd) grounds vdd is the ic power supply pin. it has a typical value of 12v and a maximum operating voltage of 16v. a zener diode circuit below 16v is recommended to guarantee that the voltage on vdd will not go any higher than 16v. the ic starts switching wh en vdd reaches 12v. the ic continues to switch as long as the vdd is higher than v dd_uvlo , which is 7v (typical). an electrolytic capacitor 22 f (typical) is recommended between vdd and grou nd to keep vdd above 7v during startup. after startup, the bias transformer winding takes over and provides enough energy to power the ic. the description of these functions can be found in section 3.2 . a 0.01-0.1 f ceramic capacitor is strongly recommended to be placed between the vdd and ic ground with the layout trace as clos e to the ic as possible. this capacitor is used for decoupling the noise to vdd and to maintain the vdd voltage during the switching of the internal driver circuit. sgnd is directly connected to the system ground by a kelvin connection trace. the system ground is the source of the mosfet, as shown in figure 28 . pgnd connects to the system ground separately and can not share the same trace wit h sgnd. this is due to pulse current on pgnd while driving the external mosfet on and off. th is pulse current produces pulse voltage drops on the pgnd trace and may cause the current sensing si gnal to be distorted if the sgnd shares the same trace. figure 28 provides layout guidelines. fb drain ocp vdd n p n s2 d r2 rgate vin isns sw sgnd d sn r sn c sn q1 pgnd keep this trace as short as possible in layout 88em8080/81 v dcin v out u3
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 52 document classification: proprietary august 6, 2010, preliminary information figure 28: vdd decoupling capacitor and ground layout guidelines fb drain ocp vdd n p n s2 d r2 rgate vin isns sw sgnd d sn r sn c sn q1 pgnd keep this trace right beside ic and as short as possible c using kelvin sensing connection for sgnd with separate trace from pgnd 88em8080/81 v dcin v out u3
design and applications information non-isolated led driver copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 53 5.7 non-isolated led driver 5.7.1 non-isolated led driver schematic figure 29: 1w non-isolated led driver schematic vin c11 1 f 25v 90vac to 264vac ? universal 47hz to 63hz non-isolated, low-cost application fb isns sgnd pgnd vdd 4 u3 sw 5 7 8 1 2 3 88em8081 r15 20 ? 1/8w d1 4.7v 500mw r14 18k vdd d9 15v 500mw r4 150k 1/2w r5 1.8m 1/2w n l l1 1.0mh hvdc c3 0.1 f 450vdc r10 150k 1w c8 0.047 f 25v r12 187 ? r22 200 ? r7 1.0 ? 1/4w c6 100pf 50v q1 650v 4.5a c2 1000pf 1kv d4 rs1j d3 stps3150rl c1 330 f 35v led + led - r20 5.6 ? 2w r17 1.91k +27.5 vdc, 450ma (nominal) c9 33 f 25v r16 18.7k d12 bat54c d7, s1m d6, s1m d5, s1m d2, s1m r21 25k t1 tran-ef16 c14 0.01 f 25v t1b r22 10 ? 1/8w d6 us1d-13-f c14 330 f 35v f1 3a c13 0.1 f
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 54 document classification: proprietary august 6, 2010, preliminary information 5.7.2 non-isolated led driver description this is a single stage non-isolated flyback led driv er with output regulation and pfc. the ac input is rectified by the diodes d2,d5,d6 and d7. fuse f1 is used for ac input over current protection. inductor l1 used for emi filtering and also helps for input surge voltage protection. resistors r5 and r14 provide the necessary voltage at vin pin for ac input voltage sensing. transformer t1 is the flyback transformer and mosfet q1 is the primary switch which is driven by marvell 88em8080/81 pfc controller through a gate resistor r15. diode d4, resistor r10 and capacitor c2 form the primary rcd clamp. resistor r7 s enses the primary current and prov ides the input to isns pin. diode d3 is the flyback diode and capacitors c1 an d c14 are the output capacitors. resistor r4 provides the initial bias for the pfc controller fr om the rectified ac input. auxiliary winding t1b provides the bias power after startup. maximum ou tput voltage protection is provided by resistors r16 and r17. the led current is sensed as the volt age across the resistor r20. the sensed output voltage from the resistor divider network r16 and r17 and the voltage across resistor r20 are both or?ed through the d12 dual diode. the output of d 12 is connected to fb pin. c13 is a decoupling capacitor. zeners d9 and d1 are used for protection. the key points for this design are: ? output -- 27.5vdc at 450ma ? universal input ? 90v to 264 vac ? dual diode for maximum output voltage protection and for sensing the led current ? small size, low cost ? maximum over voltage protection at 31vdc (typical) ? no optocoupler and no external operational amplifier ? high power factor and low thd throughout th e ac line, load and temperature ranges ? no external compensation
design and applications information isolated led driver copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 55 5.8 isolated led driver 5.8.1 isolated led driver schematic figure 30: 12.5w universal isolated led driver schematic vin c14 0.1 f 25v 90vac to 264vac ? universal 47hz to 63hz isolated applications fb isns sgnd pgnd vdd 4 u3 sw 5 7 8 1 2 3 88em8081 c9 0.1 f 25v r19 20 ? 1/8w 3 4 r11 1. 24k 1 2 d1 4.7v 500mw c5 0.01 f 25v r6 18k vdd d5 15v 500mw t1b tran-ef16 1 2 c4 22 f 25v r15 10 ? 1/ 8w d4 us1d-13-f 1 2 r9 150k 1/2w r16 866k 1/4w r13 1.0m 1/4w n l l1 1.0mh hvdc c7 c10 0.82 f, 400vdc 0.1 f, 400vdc r18 300k 1/8w r17 300k 1/8w c8 0.047 f 50v r7 187 ? r12 200 ? var1 f1 3a r5 1.0 ? 1/4w c6 100pf 50v q1 650v 4.5a c12 1000pf 1kv d10 rs1j c3 1.0nf-ycap d9 stps3150rl c11 330 f 35v c13 330 f 35v ntc1 33k r23 3.01k r10 4.02k led + led - c2 1.0 f 35v r4 4.99k r8 0.1 ? r3 4.99k r1 4.99k r2 243k u2 ts321lt 1 2 pc1a fod817a d6 15v 500mw 1 2 r22 10k r21 4.99k c1 1. 0 f 50v 12 3 vref 1 5 3 4 2 u1 tl431 +25.0 vdc, 500ma (nominal) p/o pc1a d7 s1m d8 s1m d2 s1m d3 s1m t1
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 56 document classification: proprietary august 6, 2010, preliminary information 5.8.2 isolated led driver description this is a single stage isolated flyback led driver with output regulation and pfc. the ac input is rectified by the diodes d2,d3,d7 and d8. fuse f1 is used for ac input over current protection. inductor l1 used for emi filtering and also helps for input surge voltage protection. resistors r6, r13 and r16 provide the necessary voltage at vin pin for ac input voltage sensing. transfirmer t1 is the flyback transformer and mosfet q1 is th e primary switch which is driven by marvell 88em8080/81 pfc controller through a gate resist or r19. diode d10, resistors r17,r18 and capacitor c12 form the primary rcd clamp. resistor r5 senses the primary current and provides the input to isns pin. diode d9 is the flyba ck diode and capacitors c11 and c13 are the output capacitors. resistor r9 provides the initial bias fo r the pfc controller from the rectified ac input. a secondary winding t1b of transformer t1, resistor r15, diode d4 and capacitor c4 provides the bias power to vdd pin after starting. output ovp protection is provided by zener d6. the led current is sensed as the voltage ac ross the resistor r8. this sensed voltage is amplified by u2 and then used as the input to the error amplifier u1. th e optodiode of pc1a opto coupler is connected to the output of the error amplifie r through r23, r10 and the ntc1. the opto transistor of pc1a optocoupler is connected to vdd and r11. the volt age across the resistor r11 is connected to fb pin of the controller. zeners d1, d5 and d6 are used for protection. the key points for this design are: ? output -- 25vdc at 500 ma ? universal input ? 90v to 264 vac ? high operating temperature range 0 c to 110 c ? innovative ntc compensation circuit for stable o perating point of the e rror amplifier throughout the temperature range ? small size, low cost ? over voltage protection around 27vdc ? high power factor and low thd throughout th e ac line, load and temperature ranges ? high efficiency
design and applications information isolated led driver copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 57 5.8.3 12.5w universal isolate d led driver test results a reference board has been built and test ed. the following are the test results. 5.8.3.1 efficiency and power factor the following table 9 and figure 31 provides the efficiency, power factor and total harmonic distortion data at various ac input line voltag es at full load led current of 500ma (typical). figure 31: efficiency, power factor table 9: efficiency and power factor test results input voltage (vac) input current (a) input power (w) power factor thd output voltage (v) output current (a) output power (w) efficiency (%) 90 0.17 15.272 0.999 3.00% 25.41 0.5064 12.87 84.26 115 0.133 15.04 0.999 2.92% 25.4 0.5068 12.87 85.59 135 0.113 14.95 0.998 2.97% 25.39 0.5072 12.88 86.14 180 0.0858 14.987 0.993 3.45% 25.39 0.5076 12.89 85.99 230 0.0684 15.074 0.979 7.00% 25.39 0.5082 12.90 85.60 265 0.0613 15.292 0.965 9.60% 25.39 0.5094 12.93 84.58 0.75 0.80 0.85 0.90 0.95 1.00 1.05 90 115 135 180 230 265 ac input voltage rms po w e r fa c t o r efficiency
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 58 document classification: proprietary august 6, 2010, preliminary information 5.8.3.2 start-up waveforms output voltage and input current waveforms were captured at 115ac and 230vac at full load during start-up and are shown in figure 32 and figure 33 5.8.3.3 steady state waveforms the steady state output voltage and input current waveforms were captured at 115vac and 230vac at full load and are shown in figure 34 and figure 35 figure 32: start-up at 115vac at full load figure 33: start-up at 230vac at full load figure 34: steady state at 115vac at full load figure 35: steady state at 230vac at full load
mechanical drawings mechanical drawings copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 59 6 mechanical drawings 6.1 mechanical drawings figure 36: 8-lead soic mechanical drawing notes: ? all dimensions in mm. ? see section 7, part order numbering/package marking, on page 61 for package marking and pin 1 location.
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 60 document classification: proprietary august 6, 2010, preliminary information this page intentionally left blank
part order numberi ng/package marking part order numbering copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 61 7 part order numbering/package marking 7.1 part order numbering figure 37 shows the part order numbering scheme. for co mplete ordering information, contact your marvell fae or sales representative. the standard ordering part number for the respective solution is shown in ta b l e 1 0 . figure 37: sample or dering part number xx?sag2c000?xxxx part number package code environmental code 2 = green halogen free temperature code c = commercial custom code (optional) 88em808x custom code custom code custom code table 10: 88em8080/88em8081 part order options 1 1. please note that the 88em8080 device is 60khz and the 88em8081 device is 120khz. package type part order number 8-pin soic 88em8080xx-sag2c000 8-pin soic 88EM8080XX-SAG2C000-T (tape and reel) 8-pin soic 88em8081xx-sag2c000 8-pin soic 88em8081xx-sag2c000-t (tape and reel)
88em8080/88em8081 datasheet doc. no. mv-s106340-01 rev. b copyright ? 2010 marvell page 62 document classification: proprietary august 6, 2010, preliminary information 7.2 package markings figure 38 shows a typical package marking and pin 1 location. figure 38: package marking mrvl 808x ywwg marvell company abbreviation date code and a ssembly house code y = last digit of year ww = work week g = assembly house code abbreviated part number xxxx = 4 character abbreviated part number note: the above example is not drawn to scale. location of markings are approximate. pin 1 location
copyright ? 2010 marvell doc. no. mv-s106340-01 rev. b august 6, 2010, preliminary information document classification: proprietary page 63 a revision history table 11: revision history document type document revision release 88em8080/88em8081 rev. b reworked sections: functional description and application information revised sections: ? product overview: added universal schematic and removed other two ? signal description:updated pin descriptions ? electrical characteristics: updated ec table values ? functional description: completely rewrote section (removed old content) ? application information: completely rewrote section (reworked old content) release 88em8080/88em8081 rev. a changed 30w isolated schematic release 88em8080/88em8081 rev. ? first release
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